FOUNDATION IP

The basis of anything that we create highly depends on the quality of measures we use. It is the soul of the creation. INVECAS offers a comprehensive portfolio of silicon-proven Standard Cell, Memory and GPIO libraries optimized for power, performance and area exclusively on GLOBALFOUNDRIES advanced processes to minimize integration risk, die cost and maximize SoC design flexibility for a variety of applications.

GF14LPP

Standard Cell Libraries

foundation_ip_gf14lpp_standard-cell

INVECAS standard cell libraries offer a variety of track sizes, support multiple channel lengths and a range of threshold voltage (VTs) options for performance, power and area optimization. This libraries include a base offering augmented with high performance, power management and ECO kits.

GPIO Libraries

foundation_ip_gf14lpp_gpio_libraries

INVECAS General Purpose I/O (GPIO) libraries offer a full set of cells and operating voltage ranges required to create complete I/O pad rings for SoCs. Compatible with wire bond and flip-chip packaging, the libraries include signal pads, oscillator pads, power pads, specialty pads and a full set of supporting cells (corner, filler, breaker cells, etc.). In addition, the GPIO driver pads offer Schmitt-Trigger function, programmable drive strength, pull-up/down resistors as well as HBM and CDM ESD protection.

1.2 V/1.5 V/1.8 V GPIO:

INVECAS I/O libraries support 1.2 V, 1.5 V, and 1.8 V I/O supply voltages. In-line and staggered bond pad options are supported by the design, as well the NAND-tree structure for boundary scan.

1.8 V/3.3 V GPIO:

INVECAS 3.3V GPIO library supports 1.8 V or 3.3 V I/O supply voltage, while the core circuit is designed to operate with a minimum supply voltage of 0.6 V for low power applications. In-line and staggered bond pad options are supported by the design, as well the NAND-tree structure for boundary scan.

I2C-Open Drain:

INVECAS Inter Integrated Circuit (I2C) I/O pad is an open drain bidirectional I/O cell that is designed for the two-line I2C interface. As an open drain design, this cell requires an external pull-up resistor to a power supply. The power supply (AVDD) for the pull-up is 3.3 V/5.5 V and is independent of power supply for I/O circuit (VDDIO). I2C supports Standard mode, Fast mode, Fast mode plus, High speed, and also has an option to support very high speed – 50 Mbps.

Memory Compilers

 foundation_ip_gf14lpp_memory
INVECAS offers a rich family of memory IP that includes Single-Port SRAM, Dual-Port SRAM, Time-Multiplexed Dual-Port SRAM, and Ternary Content Addressable Memories (TCAM).

Single-Port SRAM:

INVECAS Single-Port SRAM Compilers are fully synchronous single-port memory compilers implemented with multiple configuration options for performance, power and area optimization.

Dual-Port SRAM:

INVECAS Dual-Port SRAM Compilers support fully asynchronous, dual-port (2RW) memories offering users a broad range of power, performance and area optimization options.

Time-Multiplexed Dual-Port SRAM:

INVECAS Time-Multiplexed High-Performance Dual-Port SRAM compilers are fully synchronous, single-clock, dual-port memory (1R/1RW) compilers implemented as time-multiplexed single-port memory cells for a 2X area reduction compared to regular dual-port memories.

Ternary Content Addressable Memories (TCAM):

INVECAS high density, high performance TCAM compiler is designed with many integrated and user-selectable power-saving features that can significantly reduce power during search operations. These include user-selectable Field and Bank Selects to limit the search operation to only the regions specified by the user.

Memory BIST:

Custom memory BIST for INVECAS memories. Provides full featured programmable test, repair, diagnostic system for embedded memories.

GF22FDX

Standard Cell Libraries

foundation_ip_gf14lpp_standard-cell

INVECAS standard cell libraries offer a variety of track sizes, support multiple channel lengths and a range of threshold voltage (VTs) options for performance, power and area optimization. This libraries include a base offering augmented with high performance, power management and ECO kits.

GPIO Libraries

foundation_ip_gf14lpp_gpio_libraries

INVECAS General-Purpose IO (GPIO) libraries offers a full set of cells and voltage ranges required to create complete IO pad rings for SoCs. Compatible with wire bond and flip-chip packaging, the libraries include signal pads, oscillator pads, power pads, specialty pads and a full set of supporting cells (corner, filler, breaker cells, etc.,). In addition, the GPIO driver pads offer a Schmitt-Trigger function, programmable drive strength, pull-up/down resistors as well as HBM and CDM ESD protection. The libraries support 1.5 V, 1.8 V and 3.3V IO supply voltages. In-line and staggered bond pad options are supported, as well as the NAND-tree structure for boundary scan.

Memory Compilers

foundation_ip_gf14lpp_memory
INVECAS offers a rich family of memory IP that includes Single-Port SRAM, Dual-Port SRAM, Time-Multiplexed Dual-Port SRAM, Single and Dual Port Register Files, and Via ROM.

Single-Port Memories:

INVECAS Single-Port Memory Compilers are fully synchronous single-port memory compilers implemented with multiple configuration options for performance, power and area optimization. High performance, High density, Low power and Ultra low leakage compilers are available.

Multi-Port Memories:

INVECAS Multi-Port memory compilers are fully synchronous, dual-port (2RW) or two-port (1R1W) memories offering users a broad range of power, performance and area optimization options. High-performance and Low power compilers are available.

Time-Multiplexed Pseudo Multi-Port Memories:

INVECAS Time-Multiplexed Pseudo Dual-Port and Pseudo Two-Port memory compilers are fully synchronous, single-clock, dual-port (1R/1RW) or two-port (1R/1W) memory compilers implemented as time-multiplexed single-port memory cells for a 2X area reduction compared to regular multi-port memories. High-Performance, High density and Low power compilers are available.

Read-Only Memory (ROM):

INVECAS offers a High Density Via ROM compiler designed for SoC applications requiring non-volatile memories. High-Performance and Low power compilers are available.