INTERFACE IP

The Interface IP is a rich family of optimized high performance interface PHY IPs ranging from SerDes, DDR/LPDDR to MIPI and HDMI that enable SoC designs for the consumer, communications, mobile and IoT markets.

GF14LPP

Multiprotocol SERDES

sata_port

INVECAS high-speed configurable multi-protocol SerDes (Serializer/De-Serializer) supports a wide range of wireline serial interface standards from 1.25 Gbps to 12.5 Gbps for communication, networking, computing, and storage applications, providing flexibility to address various backplane and cable applications, and all with small footprint and low power consumption. Our Multi-Protocol SerDes is supplied with a companion soft block implementing the PIPE/PCS for standards like PCIe, SATA, USB and Ethernet, for seamless interoperability to the link layer or MAC logic.

DDR3/4 PHY

ip_solutions_interface_ip_gf14lpp_ddr_ddr_phy

INVECAS DDR3/4 PHY IP is provided as a hard macro fully compliant to JEDEC DDR3/DDR4 and DFI3.1. The PHY’s low jitter, low power, and high performance architecture enables data rates up to 3200MT/s. To minimize integration risk, it is submitted to rigorous silicon verification, interoperability and certification characterization.

LPDDR3/4 PHY

ip_solutions_interface_ip_gf14lpp_ddr_lp_ddr_phy

INVECAS LPDDR3/4 PHY IP is a multi-standard DRAM interface comprised of integrated PHY and I/O hard macros with a modular design that supports multiple physical configurations. It is fully compliant to JEDEC’s LPDDR3 and LPDDR4 standards, and is fully DFI 3.1 compliant. To minimize integration risk, it is submitted to rigorous silicon verification, interoperability and certification characterization.

MIPI D-PHY

ip_solutions_interface_ip_gf14lpp_mipi_d_phy

INVECAS MIPI D-PHY IP product offered as high-speed transmitter or receiver hard macros supports high-speed mode at up to 2.5Gbps data rate per lane, low-power mode at up to 10Mbps, and low-power contention detection, with best-in-class power, performance and area. Each hard macro includes Control and Interface functions compatible with the MIPI PPI interface. Our D-PHY IP is designed to be compliant with MIPI® Alliance’s D-PHY Specification v1.2 and architected for 1 to 4 data lanes, easily integrated into SOC designs, and seamlessly connected to any PPI-compliant controller for CSI-2 and DSI interfaces.

USB2.0 OTG PHY

usb_2.0

INVECAS USB Solution is a fully UTMI+ level 3-compliant USB 2.0 PHY capable of operating in Host, On-The-Go (OTG) and Device modes. Delivered as a hard macro, our solution integrates high-speed mixed-signal circuits to support 480 Mbps Hi-Speed traffic and is backward compatible to both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates.

GF22FDX

Multiprotocol SERDES

sata_port

INVECAS high-speed configurable multi-protocol SerDes (Serializer/De-Serializer) supports a wide range of wireline serial interface standards from 1.25 Gbps to 12.5 Gbps for communication, networking, computing, and storage applications, providing flexibility to address various backplane and cable applications, and all with small footprint and low power consumption. Our Multi-Protocol SerDes is supplied with a companion soft block implementing the PIPE/PCS for standards like PCIe, SATA, USB and Ethernet, for seamless interoperability to the link layer or MAC logic.

DDR3/4 PHY

ip_solutions_interface_ip_gf14lpp_ddr_ddr_phy

INVECAS DDR3/4 PHY IP is provided as a hard macro fully compliant to JEDEC DDR3/DDR4 and DFI3.1. The PHY’s low jitter, low power, and high performance architecture enables data rates up to 3200MT/s. To minimize integration risk, it is submitted to rigorous silicon verification, interoperability and certification characterization.

LPDDR3/4 PHY

ip_solutions_interface_ip_gf14lpp_ddr_lp_ddr_phy

INVECAS LPDDR3/4 PHY IP is a multi-standard DRAM interface comprised of integrated PHY and I/O hard macros with a modular design that supports multiple physical configurations. It is fully compliant to JEDEC’s LPDDR3 and LPDDR4 standards, and is fully DFI 3.1 compliant. To minimize integration risk, it is submitted to rigorous silicon verification, interoperability and certification characterization.

MIPI M-PHY

mipi_mphy

INVECAS MIPI M-PHY IP product includes high-speed transmitter or receiver hard macros supporting Gears 1-4 high-speed mode at up to 11.66Gbps data rate per lane, low-speed G0-G7 modes at up to 576Mbps with best-in-class power, performance and area. Our M-PHY IP is designed to be compliant with MIPI® Alliance’s M-PHY Specification v2.0 and architected for 1 to 4 data lanes, easily integrated into SOC designs, and seamlessly connected to MIPI CSI-3, UniPro, DigRF v4 controllers.

MIPI D-PHY

ip_solutions_interface_ip_gf14lpp_mipi_d_phy

INVECAS MIPI D-PHY IP product offered as high-speed transmitter or receiver hard macros supports high-speed mode at up to 2.5Gbps data rate per lane, low-power mode at up to 10Mbps, and low-power contention detection, with best-in-class power, performance and area. Each hard macro includes Control and Interface functions compatible with the MIPI PPI interface. Our D-PHY IP is designed to be compliant with MIPI® Alliance’s D-PHY Specification v1.2 and architected for 1 to 4 data lanes, easily integrated into SOC designs, and seamlessly connected to any PPI-compliant controller for CSI-2 and DSI interfaces.

USB2.0 OTG PHY

usb_2.0

INVECAS USB Solution is a fully UTMI+ level 3-compliant USB 2.0 PHY capable of operating in Host, On-The-Go (OTG) and Device modes. Delivered as a hard macro, our solution integrates high-speed mixed-signal circuits to support 480 Mbps Hi-Speed traffic and is backward compatible to both Full-Speed (12 Mbps) and Low-Speed (1.5 Mbps) data rates.

HDMI TX PHY

HDMI-Port

The INVECAS HDMI 2.0 TX PHY is a high-speed, mixed-signal PHY IP optimized on GLOBALFOUNDRIES process for high performance, low power and small area. At speeds up to 6Gbps, our standard compliant, silicon-proven solution enables designers to accelerate time-to-market and reduce integration risk for next-generation consumer electronic applications. Our HDMI TX IP is fully compliant to the HDMI specifications, and has gone through extensive in-house and third-party interoperability testing.

HDMI RX PHY

HDMI-Port

The INVECAS HDMI 2.0 RX PHY is a high-speed, mixed-signal PHY IP optimized on GLOBALFOUNDRIES process for high performance, low power and small area. At speeds up to 6Gbps, our standard compliant, silicon-proven solution enables designers to accelerate time-to-market and reduce integration risk for next-generation consumer electronic applications. Our HDMI RX IP is fully compliant to the HDMI specifications, and has gone through extensive in-house and third-party interoperability testing.