INVECAS Achieves Predictable Design Convergence with Cadence Tempus Timing Signoff Solution

Cadence technology enables INVECAS to accelerate time-to-tapeout by up to three months

Hyderabad, India – November 11, 2019  — INVECAS Inc, a leading provider of IP and ASIC design solutions, today announced that it has successfully integrated the Cadence Tempus Timing Signoff Solution into their Advanced Chip Builder Tool (ACT™) physical implementation flow to achieve predictable design convergence for a wide range of customer ASIC designs, while accelerating time-to-tapeout by up to three months.

INVECAS provides IP solutions in advanced nodes like 22nm FDSOI and 14/12nm FINFET technologies for key global customers targeting next generation AI, 5G, IoT, automobile and networking markets. The ASIC designs targeting these market applications are complex designs with multiple hierarchies featuring 1B-2B+ gate count, high performance and low power. INVECAS customers expect faster time to market for their ASIC product deployment, which drives the need for faster design convergence and a reduction in overall design cycle time from netlist to GDSII on these large designs.

“Timing convergence is a critical task and often the long pole for design closure. INVECAS deployed the Cadence Tempus Timing Signoff Solution for all ASIC timing convergence and signoff, tremendously helping engineers to overcome the challenges with ease and work towards predictable design closure.” said Srinivasa Gutta, VP of engineering, INVECAS.

The Cadence Tempus Timing Solution provides full-chip timing signoff as well as timing ECO and optimization. It is integrated with the Cadence Innovus Physical Implementation System, which utilize the same timing engines, enabling INVECAS to achieve excellent timing correlation and faster timing convergence with fewer ECO iterations. INVECAS also reduced implementation turnaround times by leveraging the Cadence Tempus Boundary Models for hierarchical modeling of sub-blocks without any significant losses in accuracy. As designs keep getting bigger, it is critical to have a scalable timing methodology that will satisfy static timing analysis (STA) throughput needs for future technology nodes. The Tempus Boundary Models and Cadence SmartScope hierarchical abstraction models provide an easy and accurate way to take advantage of the hierarchy without adding big safety margins and extra iterations to converge to final timing signoff closure.

“Time to market is critical in a fast-paced, competitive semiconductor market. The big complex designs in deep sub-micron technologies require access to large server farms to keep pace with memory size requirements and the number of the corners and modes (100) to close the timing in a predictable manner within a reasonable window with fewer iterations. This requires innovative approach towards planning STA runs and improving the STA throughput for final signoff. Cadence’s Tempus Timing Signoff Solution, with features like Boundary Models and distributed STA, lets us tape out designs two to three months faster compared to traditional approaches.” added Srinivasa Gutta, VP of engineering, INVECAS.

“INVECAS is creating complex, advanced-node ASICs for highly competitive markets, and having the ability to accelerate time to market is critical for their success. The Cadence Tempus Timing Signoff Solution is foundry-certified and offers INVECAS a comprehensive set of advanced capabilities and the industry’s fastest STA to address their design requirements, enabling them achieve SoC design excellence,” said KT Moore, vice president, product management in the Digital & Signoff Group at Cadence.

About INVECAS, Inc.

Headquartered in Santa Clara, CA, INVECAS is a leading provider of silicon-proven and standards compliant IP and custom IC solutions. The INVECAS team has driven the creation of the highly successful HDMI® industry standard through its direct participation in HDMI
standards bodies. Via its subsidiary, Simplay Labs ATC LLC, INVECAS offers manufacturers comprehensive standards interoperability and compliance testing services. Additionally, expertise in ASIC & Design Services, Embedded Software & System-level Solutions, make INVECAS a one-stop-destination for EDMs working on diverse market segments. For more information, visit . https://www.invecas.com/

INVECAS and the INVECAS logo are trademarks, registered trademarks or service marks of INVECAS, Inc. in the United States and/or other countries. All other trademarks and registered trademarks are the property of their respective owners.

SOURCE : Sheela Panicker, Media Contact for INVECAS, +91 98498 09594, sheela@enrightpr.com

 
x
This website uses cookies to ensure you get the best experience on our website. Learn More . Got It