INVECAS Design Realization team has proven expertise and experience to assist in design feasibility and performance evaluation, architecture, integration, verification and physical design of most complex SoCs for the computer, communications, consumer, automotive, and IoT markets.
Logic Design & Verification
INVECAS Design Realization team has proven expertise and experience to assist in design feasibility and performance evaluation, SoC architecture, integration, and verification. We’ve worked directly on bus interconnect protocols, integration of various processor cores, security mechanisms.
With broad experience, best practice and protocol expertise in functional verification for IP and complex SOCs. Our verification engineers can build and deploy complex verification environments tailored to customer’s specific requirements to minimize functional bugs and speed up his SoC time to market.
INVECAS offers IP and SOC verification environment solutions are based on industry standard tools, languages (Verilog, System Verilog & C/C++) and methodologies (UVM, OVM) from leading EDA vendors like CADENCE, SYNOPSYS and MENTOR. For IP and SoC, INVECAS can help with verification planning, including architecture for re-use, low power static verification, formal verification, test bench generation, and integration of protocol-specific VIP.
INVECAS physical design experts help customers meet the challenges of the growing number and complexity of IP blocks and subsystems in today’s SoCs. We map product requirements to our in-house SOC-HP and SOC-LP design flows and tailor additional options for further design optimization. We combine our other in house add-on flows and methodologies like Advanced Chip Builder (ACT)™, Smart Power™ and Rapid Characterization Engine (RaCE)™ to deliver SoC designs on time and meeting all required parameters. Our physical design team is skilled in SoC configuration, integration of complex IP subsystems, and possesses extensive knowledge of industry standard physical design tools. The team has executed multiple projects at all nodes up to 14nm.